The present invention relates in general to interconnect structures in electronic circuitry, and in particular to a method of filling via holes between two conductive layers using the underlying conductive layer.
In semiconductor processing and certain types of printed circuit boards, vias are used to provide electrical connection between two conductive layers such as metal that are separated by a layer of insulating material (inter-layer dielectric, ILD). Typically, a film containing a conductive layer such as aluminum is deposited on a substrate. After a step of patterning the first layer, an insulating film (ILD) is formed on top of the first conductive layer. Via holes are then opened to expose the underlying first layer in desired locations. The second conductive layer is then deposited on top of the insulating layer, filling the vias to make electrical contact with the first conductive layer.
There are problems associated with conventional methods of filling via holes. In semiconductor processing, for example, the second conductive layer, typically aluminum (Al) is commonly deposited on top of the insulating material by a sputtering step. The second aluminum layer tends to form in a non-uniform fashion around the via hole as it is sputtered over the via opening. FIG. 1A demonstrates the typical shape that results from the sputtering action. Shadowing causes metal thickness to thin at the bottom edges and sides of the via hole. This type of non-uniform step coverage is exaggerated for smaller geometries where the via hole has higher aspect ratio. FIG. 1B illustrates the type of defect that may arise as a result of this process. The sputtering action may cause a gap inside the via hole, failing to provide an electrical contact between the two conductive layers.
The step coverage problem associated with sputtered metal can be improved by sloping the sidewalls of the via. Vias with sloped sidewalls, however, take more area compared to vias with straight sidewalls. Further, straight sidewalls are easier to form using conventional dry etching processes than sloped sidewalls.
Increasing deposition temperatures has shown to improve the step coverage. Deposition at higher temperatures yields a more uniform thickness over the via due to surface migration of the atoms and their tendency to rearrange themselves in a more uniform fashion. The coverage, however, remains a problem as the dimensions get smaller and the aspect ratios get larger.
Improvements in via process technology have been developed that use tungsten (W) in combination with various other steps to plug the via hole. The resulting structure shows good conformal coverage of the topography. The tungsten plug process, however, tends to be more complex and involves more steps. Because tungsten does not adhere well to the oxide insulating layer, it has been necessary to use a thin film of, for example, titanium nitride (TiN) that is deposited first to act as a "glue" layer between the tungsten and the insulating layer. FIG. 2 illustrates a tungsten plugged via using TiN glue layer. In addition to the added processing steps, the resulting via resistance is increased.
As the ever shrinking feature sizes head into the submicron regime and the aspect ratio of via holes increases, fabricating the optimum via structure becomes more challenging. There is a need for a cost effective and efficient method of filling via holes.